Such a method is disclosed for example in the published US Patent Application Publication No. 2003/0201481 A1, and is used for fabricating a DRAM memory cell. In this previously known method, firstly a capacitor as passive component is integrated into a silicon substrate. The capacitor is a so-called deep trench capacitor. An elevated silicon region having a surface and sidewalls adjoining the latter is formed directly alongside the capacitor. A field effect transistor is formed in the region of the surface of the elevated region and also at a sidewall of the elevated region that faces the deep trench capacitor, the gate region of the field effect transistor being arranged at the sidewall of the elevated region. For the purpose of covering the capacitor and for insulating the capacitor from an electrical drive line of the DRAM memory cell, the capacitor is insulated by means of an insulation layer, namely an STI layer (STI: Shallow Trench Insulation).